Method for direct access test of embedded cells and customization logic

ABSTRACT

Methods and related structures for both operating and testing an integrated circuit constructed of combinations of customization logic and embedded cells. Functional modes include an operational mode and a test mode with two submodes. Test terminals of embedded cells, as well as test points in customization logic, are both accessed via a multiplexing scheme using test points of x-y (row and column) wiring traces of a grid-based &#34;cross-check&#34; test structure for both logic testing and embedded cell testing. Common conductors or traces can be used to operate the embedded cells and to control the made and test the embedded cells and customization logic. The x and y lines can be operated as signal lines, as probe lines, as sense lines and as control lines, as needed, using multiplexing according to the invention. In addition, the x and y lines can be used, in connection with analog multiplexers and switches, to probe, stimulate and sense embedded analog signal circuits, subsystems and conditions of an embedded cell. In a case where multiple probe lines are active, test points are held in a high impedance state by placing the clock of latches or flip flops at the intersections of the sense lines and the probe lines in a suspended state and applying only half the switching voltage to the line operative as the sense line. Such latches also permit testing in the presence of asynchronous signals.

This is a Continuation of application Ser. No. 08/726.726, filed Oct. 7,1996 now abandoned, which is a Continuation of application Ser. No.08/330.888, filed Oct. 28. 1994 now abandoned, the disclosure of whichis incorporated by reference.

BACKGROUND OF THE INVENTION

This invention relates to testing of integrated circuits. In particular,this invention relates to testing of embedded structures and customizedstructures in very large scale integrated circuits (VLSI circuits) whichpermit direct access testing of subsystems within VLSI circuits.

Eliminating flaws in the design of an integrated circuit before movinginto the production phase is a costly and time consuming process. Due todesign errors, fabrication errors, timing problems, or incompletespecifications, many ICs fail to fully perform the task for which theyare designed when they are initially integrated into a system. Onesolution has been so-called built-in self testing or embedded testing.

One form of embedded testing of VLSI circuitry is based on the use of agrid of test points at the intersections of x and y (row and column)conductive lines overlaying a VLSI "cloud" of circuitry integrated intoa chip. Reference is made to U.S. Pat. No. 4,749,947, issued Jun. 7,1988, entitled GRID-BASED, "CROSS-CHECK" TEST STRUCTURE FOR TESTINGINTEGRATED CIRCUITS, inventor Tushar Gheewala for background. Referringto FIG. 1, there is shown a prior art grid-based, "CrossCheck®" teststructure 10 used in methods for testing random logic circuits in anintegrated circuit, as disclosed in U.S. Pat. No. 4,749,947 owned by theassignee of the present invention. Therein, a grid 12 of test points 14is accessed by addressable sets of X and Y wiring traces with the Ydirection therein for sense lines S₁ . . . S_(N) and with the Xdirection for probe lines P₁ . . . P_(N) Traces functioning as probelines P₁ . . . P_(N) select which row (column) of test points 14 is tobe accessed, and the sense lines S₁ . . . S_(N) read the signal from theselected column (row). In one known embodiment of the prior art, thesignals applied through a single input port or pin 31 are applied to thesense lines S₁ . . . S_(N) through shift register 28, and data read fromthe test points 14 by the sense lines S₁ . . . S_(N) are fed to a shiftregister 28 from which the data can be read out through a singleinput/output (I/O) pin or pad 32, thus minimizing the number of pinswhich must be dedicated to diagnostics. Because only one port wasavailable to extract data, thus slowing down throughput, one solutionsuggested has been the use of a linear feedback shift register (LFSR) asa means to compress the data and to generate a signature representationof the data. Because some diagnostically useful information is lost inan LFSR, a need has existed to improve on the prior art techniques.

In other prior art, use has been made of added on-chip test electronicsor additional I/Os to access the grid.

One class of circuits which would benefit from in-circuit testing is theembedded cell. An embedded cell is usually a precharacterized andpredesigned integrated circuit subsystem designed in many cases with adifferent design technique and requires a test methodology differentfrom that of the surrounding circuitry. Embedded cells are subsystemdesigns which are not designed at the outset for testability from theperiphery of the integrated circuit (IC) structure. Examples are SRAMs,ROMs, ALUs, microprocessors, and communication interfaces. In the past,additional custom wiring had to be added (or "written" on the IC) toembedded cells to provide access to internal test points from externalconnections. This wiring was in addition to that required for testingthe non-embedded cells, or what is generally referred to ascustomization logic. This solution caused an undesired increase in areato an integrated circuit.

In the prior art, there have been two classes of test methodologies. Onewas based on use of a grid pattern. This class is represented by U.S.Pats. 4,747,947 (to CrossCheck Technology) and 4,613,970 (to Hitachi)and by European Patent Publication 174,236 (to Fujitsu). None explainhow a grid could be used to test embedded cells. Another class oftesting methodology is represented by U.S. Pat. No. 5,331,571 issuedJul. 19, 1994 to NEC Electronics, Inc. of Mountain View, California, anda publication entitled Multiplexed PMT Application Note (undated,copyright 1994) of Texas Instruments. In the last reference,multiplexers are used to connect, in the test mode, embedded cellinput/output terminals to IC periphery pads so that tests can be appliedto the embedded cells from the pads of the periphery.

However, the prior art does not teach or suggest how to use multiplexingto form a grid of traces for use in operating and testing both embeddedcells and customization logic, which is the subject of the presentapplication. Methods and apparatus are needed for testing integratedcircuits with embedded cells which minimizes need for additional wiringtraces and complexity necessary to access test points within embeddedcells.

SUMMARY OF THE INVENTION

According to the invention, methods and related structures for bothoperating and testing an integrated circuit constructed of combinationsof customization logic and embedded cells are disclosed in which threemodes of operation are provided. Test terminals of embedded cells, aswell as test points in customization logic, are both accessed via amultiplexing scheme using test points of x-y (row and column) wiringtraces of a grid-based "cross-check" test structure for bothcustomization logic testing and embedded cell testing. The same tracescan be used to carry mode control signals for the multiplexers, probe"select" signals and probe "test" signals for the customization logic aswell as the embedded cells, and sense line (test output) signals, aswell as the signals which operate and test the embedded cells. Thegrid-based test structure may be modified at the design and layoutstages to allow row and column traces to be rerouted around thelocations of embedded cells without disrupting the underlying addressingscheme of a grid based system. In the method, multiplexing of the x andy wiring adjacent the embedded cells allows switching betweenoperational mode and two test modes (employing logic circuit testprotocols and embedded cell test protocols), and the sense and probefunctions of the x and y wiring can be interchanged. The x and y linescan be used, in connection with analog multiplexers and analog switches,to probe, stimulate and sense embedded analog signal circuits,subsystems and conditions of an embedded cell.

A special input-data-hold latch is preferably disposed at selected testpoints of the grid and multiplexed between the customized logic testmode and the operational mode to allow for the probing of internal nodeswhich are held constant during a mode switch operation. Such latchesalso permit testing in the presence of asynchronous signals.

A further understanding of the nature and advantages of the presentinvention may be realized by reference to the remaining portions of thespecification and the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a prior art test structure.

FIG. 2 is a block diagram of a specific embodiment of the presentinvention showing signal paths for testing.

FIG. 3 is a schematic block diagram of a specific embodiment of thepresent invention showing signal paths for a common test enable signalfor both an input and an output from an operational circuit.

FIG. 4 is flow chart for a test method useful for testing according toone aspect of the invention.

FIG. 5 is a block diagram for illustrating direct observation ofinternal analog signals according to the present invention.

FIG. 6 is a flow chart illustrating the method for constructing anintegrated circuit according to the invention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Referring to FIG. 2, this invention solves problems of the prior art ofgrid-based testing of an integrated circuit 110 by providing in itsdesign direct access to sense lines S₁ . . . S_(N) and probe lines P₁ .. . P_(N) for testing both grid-based customization logic 112 andembedded cells 114 by use of first multiplexers (X) 118 at input/outputports or pads 120, 140 of an integrated circuit between the signal lines(not shown) and grid lines 160, 180 serving as the sense lines S₁ . . .S_(N) and probe lines P₁ . . . P_(N), and also by providing multiplexers122 adjacent the test terminals of embedded cells 114 in the circuitdesign also serving as switches between signal lines and the same senseline/probe lines. Two types of circuitry are represented on theintegrated circuit 110: customization logic elements 112 and embeddedcells 114. Embedded cells 114 are precharacterized circuit designs whichgenerally require a test methodology different from that of thesurrounding circuitry. Embedded cells 114 are not designed at the outsetfor testability from the periphery of the layout area. On the otherhand, grid-based testing employs probe lines P₁ . . . P_(N) to selectelements of customization logic to test, and it also employs sense linesS₁ . . . S_(N) to supply excitation signals and/or observe responses toexcitation signals. In accordance with a specific aspect of theinvention, a latch and preferably a specific type of latch, hereinreferred to as a suspendable state latch 200, is designed into thecustomization logic 112 to connect with intersections of grid lines 160and 180 to access test points 115 in the customization logic. Thesuspendable state latch 200 is preferably controllable by a clock input116 (accessed by clock traces--not shown). A more complete descriptionof one embodiment of a suspended state latch in accordance with theinvention is found in U.S. patent application Ser. No. 07/929,873 filedAug. 11, 1992 in the name of Tushar Gheewala entitled METHOD ANDAPPARATUS FOR TESTING AN INTEGRATED CIRCUIT, the description of which isincorporated herein by reference. These suspended state latches canreceive at least two inputs and can provide at least two outputs, one ofthe ports 261 being bidirectional.

Three distinct operational states of the multiplexers 118 and 122 arerecognized: Disable Test State (Operation State), Enable Test State 1(Customization Logic Test) and Enable Test State 2 (Embedded Cell Test).These states will be apparent from the following description.

FIG. 3 shows the connections of sense lines 160 and probe lines 180 topads 120 and 140 through multiplexers 118. The multiplexing switches 118are controlled by a Chip Test Enable signal applied via test pad 185 online 125. The Chip Test Enable signal also controls an input stateretention latch 131, as hereinafter explained.

In the operational mode, Test Enable is held OFF, disconnecting theprobe/sense line 160, 180 from pads 120, 140. In this mode, latches 131are in "transparent" mode, connecting input 140 directly to theoperational circuit 321. There is a test mode upon application of theChip Test Enable signal 125. There are two test submodes, one fortesting customization logic and one for testing of embedded cells.

In either test submode, Test Enable (125) is turned ON, the input dataon input pads 140 are latched into the state retention latches 131, andtypically all test lines 160, 180 are connected through multiplexers118. Test patterns can now be applied to or observed from sense andprobe lines 160, 180 now connected directly to the signal pads 120 and140 at the edge of the chip 110.

FIG. 3 further illustrates the specific test submodes. To testcustomization logic in the first test submode, only the chip test enablesignal 125 needs to be active. This in turn connects input/output pads120, 140 to sense lines 160 and probe lines 180 through switches 118.The external inputs to the operational circuit 112 are held by stateretention latches 131. To test an internal circuit, for example 212,signals can now be applied to the internal suspendable state latches 200using probe lines 180 and sense lines 160. Thus in the first testsubmode, the input/output pads are used to control and observe sense andprobe lines, which in turn control internal storage elements to applytest patterns to internal circuits and also to observe the resultingsignals to check if the circuit has any defects in it. The internal testpoints are located at the intersections of the sense and probe lines,where the suspendable state latches are also located. In a compactdesign, the test points are embedded in the suspendable state latches200 to be activated selectively to observe output lines 170, 171.(However, the test points need not be located exclusively at thelatches. There may be additional test points, such as observation pointson the chip. All test points need not be at suspendable state latches.In certain applications, simple multiplexers might be satisfactory sitesof test points. Since a chip design is expected to take into account atsome level the nature of the test structures, adaptations of a basictest structure design are contemplated.)

The second test submode for testing embedded cells is also shown in FIG.3. An embedded cell 114 may be operationally connected directly to thecustomization logic or connected via a suspendable state latch 200 asshown through a mux 122 adjacent the embedded cell 114. A second testenable signal, cell test enable signal TE1 126 is applied, in additionto the chip test enable signal TE 125. TE1 is used to switch theembedded cell explicitly into the second test submode. TE1 also controlsmultiplexing switches 122. Switches 122 route signals to and fromselected external test pads 120 and 140 and disconnect the embedded cell114 from other internal circuitry, such as the customization logic 112,when TE1 is ON, isolating the embedded cell from operational circuits.Thereupon, the embedded cell 114 can be directly tested by applicationof test signals at chip pads 120, 140, without interference from theoperational circuits connected to it. (The mux mechanisms at the signalpads and near cell test terminals may be latches acting as multiplexersbetween two test modes.)

To test a RAM 209 representing an embedded cell 114, signals may beapplied directly from chip pads 120, 140 to inputs via muxes 122 in adirect access state. It is interesting to note that the probe lines andsense lines may have dual functions and further that the probe lines andsense lines may be physically routed around the embedded cell. In therespective test submodes, the sense lines and probe lines play differentroles. In testing of customization logic, the probe lines control whichtest point is activated, while the sense lines apply test data andobserve applied test data. In the embedded cell test submode, the probelines and the sense lines can be used to both apply and observe testsignals. While in FIG. 3, Test Enable 1 (TE1) is shown to be controlledvia a signal TE through TE line 125, the signal TE1 could be generatedor controlled by any internal or external signal. Similarly, the signalTE could be internally generated.

Specifically, it may be noted that in the first test submode (test ofcustomization logic), sense lines 160 are used both for writing intosuspendable state latches 200 and for reading from the suspendable statelatches 200 whereas the probe lines 180 are used only to select thesuspendable state latches 200 for access through sense lines 160. Incontrast during the second test submode (test of embedded cells) senselines 160 and probe lines 180 may be used for conducting test signalsfrom input/output pads 120, 140 into the cell under test as well as forconducting test responses from the cell to pads 120, 140. In order to beable to access suspendable state latches and embedded cells during test,the sense and probe lines may be physically routed around, over orthrough the embedded cells 114.

It should be noted that while reading from the input of an asynchronousor level-sensitive latch (as opposed to flipflops) the output of thelatch may be driven momentarily to a value different from the one it issupposed to hold. This may occur due to the large capacitance of thesense line being driven at this input as compared to the capacitanceoffered by the inverter input. Such a momentary change of value isreferred to as a "hazard." In the event of such a hazard, otherasynchronous or level-sensitive sequential elements in the circuit maychange their state to one that is different from the expected state. Dueto this reason, a special method is necessary to assure that hazards donot occur while reading from the inputs of level-sensitive orasynchronous latches. Referring to FIG. 4, this method is to anticipatethe value of the internal test point by running logic simulation duringtest program development (Step A). Before reading input values oflevel-sensitive or asynchronous latches the expected logic valuesobtained from such simulation, are applied on the sense lines through IOpads (Step B). During the read operation, if the latch input value isthe same as expected (indicating no error) then there is no hazard atthe latch output. However, if the latch input is in error, having avalue opposite to that expected, the sense line is charged to thiserroneous value by the input source. This erroneous value is then to beread from the IO pad connected to the sense line.

One of the features of direct access diagnostics is illustrated in FIG.5, which is a block diagram for illustrating direct observation ofinternal analog signals according to the invention. Probe line P₁ andsense lines S₁, S₂ S₃ have at their intersection 300 a transmission gateswitch 302 connecting analog devices 301 to the S test grid wiringtraces. Further, the grid is connected to analog test points 304, 306,308 from which from analog signals can be observed externally withappropriate analog test instruments, such as receivers 310, 312 andanalog analyzers 313. The analog test points 304, 306, 308 areaccessible through CMOS transmission gates 305, 307, 309 forming analogswitches acting as muxes. In addition, other multiplexers (not shown)used to access the sense lines and probe lines need to be able tosupport analog signals. In this manner, it is possible to directlyobserve analog signals, relative timing and even power supply noise.

One of the aspects of the invention is the design protocol for designingan integrated circuit incorporating the features permitting the built intestability. Referring to FIG. 6 a combination of steps which is knownin the art is combined in a new method for designing the internallytestable integrated circuit containing customization logic elements andembedded cell circuitry. The new method involves the steps of firstdesigning electrical aspects of the basic integrated circuit withoutreference to signals traces forming a grid overlay to obtain a basicnetlist for a basic integrated circuit design (Step C). Then laying outbasic integrated circuit design with attention to optimized signal lineinterconnects and optimized signal delays to obtain a basic circuitlayout (Step D). This is a conventionally automated process for whichcommercial products are available. Thereafter, synthesizing asupplemental netlist of input and output signal trace connections totest points and test pads within the basic circuit layout (Step E). Thissupplemental netlist is built with attention to optimized distancebetween selected unique input and output connections and the test pointsand pads. Then the supplemental netlist is appended to the basic netlistto obtain a composite netlist (Step F), and a routing protocol is run orinvoked on the composite netlist to obtain a composite integratedcircuit design (Step G). The placement of the functional circuitcomponents and subsystems remains stable, but the new layout may in somecases result in rerouting of wiring traces according to the invention.

While the invention has been particularly shown and described withreference to a specific embodiment thereof, it will be understood bythose skilled in the art that the foregoing and other changes in theform and details may be made therein without departing from the spiritor scope of the invention.

What is claimed is:
 1. In an integrated circuit having a grid pattern ofaddressable rows and columns of grid lines and having both customizationlogic elements and predesigned embedded cells said predesigned embeddedcells having test points at least at their inputs and outputs, said testpoints being specified within a contained cell region and havingassociated therewith a predesigned cell test protocol differing from acustomized test protocol for said customization logic elements, a methodfor testing the integrated circuit comprising the steps of:a) applyingcontrol signals to deselect an operation mode and to select a testenable mode, wherein, in said test enable mode, first multiplexing meansprovide connections between selected grid lines in said integratedcircuit and signal pads at edges of said integrated circuit and provideconnections to selected locations which are adjacent test pads and testpoints within said integrated circuit; b1) selecting a first testsubmode corresponding to said customized test protocol; b2) providingstate suspendable latch means between a selected one of said grid linesand selected ones of said test points; in said first test submode, c)applying probe signals via first selected grid lines in said integratedcircuit, said first selected grid lines being operative as probe linesand coupled through said first multiplexing means to said test points toaddress at least one of said test points in said customization logic; d)in accordance with said customized test protocol, selectively applyingfirst excitation signals to said customization logic and detectingoutput signals from said customization logic elements via secondselected grid lines, said second selected grid lines being operative assense lines; and e) selecting a second test submode corresponding tosaid predesigned cell test protocol; in said second test submode, (f) inaccordance with said predesigned cell test protocol, selectivelyapplying a test enable signal as a probe signal to activate all testpoints of input and output terminals of each selected predesignedembedded cell and thereafter applying second excitation signals to testterminals of said predesigned embedded cells via selected ones of saidfirst and second selected grid lines, wherein at least one type of saidfirst and second selected grid lines normally limited to carrying aunidirectional address signal as a probe line in said first test submodeis configured for carrying bidirectional data signals as a sense line;and g) receiving output signals from said embedded cells in response tosaid second excitation signals via said one type of selected ones ofsaid first and second selected grid lines.
 2. The method according toclaim 1 wherein at least said first selected grid lines and said secondselected grid lines are addressable row lines and addressable columnlines, andwherein said second test submode selecting step comprisesconfiguring selected second multiplexing means coupled to said externalterminals to provide signal paths for said probe lines of said firsttest submode as bidirectional sense lines of said second test submode toselected test points of said embedded cells.
 3. The method according toclaim 1 wherein probe signals are protected from causing sense lineconflict, further including the steps of:invoking a suspended state ofsaid latch means to cause said test points and test pads coupled to saidselected one of said sense lines to float; applying a half voltagesignal to said selected one of said sense lines; applying a probe signalvia a selected probe line to invoke a response on said selected one ofsaid sense lines; and removing said suspended state to propagate senseline signals through said latch means.
 4. The method according to claim3 wherein analog signal components are rendered testable, furtherincluding the steps of:routing analog signals through said firstmultiplexing means.
 5. An integrated circuit having a grid pattern ofaddressable rows and columns of grid lines and having both customizationlogic elements and predesigned embedded cells, said redesigned embeddedcells having test points at least at their inputs and outputs, said testpoints being specified within a contained cell region and havingassociated therewith a predesigned cell test protocol differing from acustomized test protocol for said customization logic elements, saidintegrated circuit further comprising:a) a plurality of firstmultiplexing means adjacent signal pads of said integrated circuitdefining switchable connections between selected grid lines in saidintegrated circuit and signal pads of said integrated circuit anddefining switchable connections to selected locations which are testpoints of said customization logic; b) a plurality of secondmultiplexing means at selected locations in said integrated circuitdefining connections between selected grid lines and alternately testpoints of said embedded cells and said test points of said customizationlogic, a set of said selected grid lines being operable as bidirectionalsense lines when said second multiplexing means connect said selectedgrid lines to said test points of said predesigned embedded cells; c)probe signal applying means provided via a test enable signal line tosaid multiplexing means, to enable testing of said predesigned embeddedcells; and d) state suspendable latch means between a selected one ofsaid grid lines and selected ones of said test points.
 6. The integratedcircuit according to claim 5 wherein said signal points providing directconnections to test points and test points for test signals appliedexternal of said integrated circuit.
 7. The integrated circuit accordingto claim 5 wherein at least selected ones of said plurality of firstmultiplexing means is configured to connect between a single signal padof an integrated circuit and a plurality of adjacent grid lines.
 8. Anintegrated circuit having a grid pattern of addressable rows and columnsof grid lines and having both customization logic elements andpredesigned embedded cells, said predesigned embedded cells having testpoints at least at their inputs and outputs, said test points beingspecified within a contained cell region and having associated therewitha predesigned cell test protocol differing from a customized testprotocol for said customization logic elements, said integrated circuitfurther comprising:a) a plurality of first multiplexing means adjacentsignal pads of said integrated circuit defining switchable connectionsbetween selected grid lines in said integrated circuit and signal padsof said integrated circuit and defining switchable connections toselected locations which are test points of said customization logic; b)a plurality of second multiplexing means at selected locations in saidintegrated circuit defining connections between selected grid lines andalternately test points of said embedded cells and said test points ofsaid customization logic, a set of said selected grid lines beingoperable as bidirectional sense lines when said second multiplexingmeans connect said selected grid lines to said test points of saidpredesigned embedded cells; and a plurality of state suspendable latchmeans between selected sense lines and selected ones of said test pointsto permit tentative loading of said sense lines during a test protocol.9. An integrated circuit having a grid pattern of addressable rows andcolumns of grid lines and having both customization logic elements andpredesigned embedded cells, said predesigned embedded cells having testpoints at least at their inputs and outputs, said test points beingspecified within a contained cell region and having associated therewitha predesigned cell test protocol differing from a customized testprotocol for said customization logic elements, said integrated circuitfurther comprising:a) a plurality of first multiplexing means adjacentsignal pads of said integrated circuit defining switchable connectionsbetween selected grid lines in said integrated circuit and signal padsof said integrated circuit and defining switchable connections toselected locations which are test points of said customization logic;and b) a plurality of second multiplexing means at selected locations insaid integrated circuit defining connections between selected grid linesand alternately test points of said embedded cells and said test pointsof said customization logic, a set of said selected grid lines beingoperable as bidirectional sense lines when said second multiplexingmeans connect said selected grid lines to said test points of saidpredesigned embedded cells; wherein said first multiplexer means permitpropagation of signals of analog signal levels and further includinganalog storage means on said sense lines and to permit temporary storageof analog signal values during a test protocol.
 10. In an integratedcircuit having a grid pattern of addressable rows and columns of gridlines and having both customization logic elements and predesignedembedded cells, said predesigned embedded cells having test points atleast at their inputs and outputs, said test points being specifiedwithin a contained cell region and having associated therewith apredesigned cell test protocol differing from a customized test protocolfor said customization logic elements, a method for testing theintegrated circuit comprising the steps of:a) applying control signalsto deselect an operation mode and to select a test enable mode, wherein,in said test enable mode, first multiplexing means provide connectionsbetween selected grid lines in said integrated circuit and signal padsat edges of said integrated circuit and provide connections to selectedlocations which are adjacent test pads and test points within saidintegrated circuit; b) selecting a first test submode corresponding tosaid customized test protocol; in said first test submode,c) applyingprobe signals via first selected grid lines in said integrated circuit,said first selected grid lines being operative as probe lines andcoupled through said first multiplexing means to said test points toaddress at least one of said test points in said customization logic; d)in accordance with said customized test protocol, selectively applyingfirst excitation signals to said customization logic and detectingoutput signals from said customization logic elements via secondselected grid lines, said second selected grid lines being operative assense lines; and e) selecting a second test submode corresponding tosaid predesigned cell test protocol; in said second test submode,(f) inaccordance with said predesigned cell test protocol, selectivelyapplying second excitation signals to test terminals of said predesignedembedded cells via selected ones of said first and second selected gridlines; and g) receiving output signals from said embedded cells inresponse to said second excitation signals via selected ones of saidfirst and second selected grid lines; wherein probe signals areprotected from causing sense line conflict, further including the stepsof:providing state suspendable latch means between a selected one ofsaid sense lines and selected ones of said test points and test pads;invoking a suspended state of said latch means to cause said test pointsand test pads coupled to said selected one of said sense lines to float;applying a half voltage signal to said selected one of said sense lines;applying a probe signal via a selected probe line to invoke a responseon said selected one of said sense lines; and removing said suspendedstate to propagate sense line signals through said latch means.